Semiconductor-on-insulator (SOI) technology provides several advantages over conventional bulk silicon technology for integrated circuit (IC) structures for radio frequency (RF), low power, and high performance applications. These advantages include reduced processing steps, CMOS circuit latchup elimination, parasitic capacitance reduction for increased speed, improved device isolation, and superior radiation hardness.
FIG. 1A is a cross-sectional view of a conventional SOI structure 100. An active semiconductor layer (device layer) 102 overlies an isolation layer, typically a buried oxide layer 104, which in turn overlies a substrate 106. The thickness of active semiconductor layer 102 for a conventional SOI structure 100 being considered here is generally of the order of less than 400 nm and typically of the order of approximately 200 nm, and the thickness of buried oxide layer 104 is generally less than 1,000 nm and typically of the order of approximately 400 nm. In some conventional SOI structures, substrate 106 has P-type conductivity, whereas in other SOI structures, substrate 106 has N-type conductivity. Similarly, in some SOI structures, active semiconductor layer 102 has P-type conductivity, whereas in other SOI structures, active semiconductor layer 102 has N-type conductivity.
Active semiconductor layer 102 includes active and passive integrated circuit elements, contact regions and interconnects, which are isolated from substrate 106 by buried oxide layer 104. FIG. 1B is a cross-sectional view schematically illustrating a conventional passive element (e.g. conventional inductor 152) in a conventional SOI structure 150. There are numerous methods familiar in the art for forming conventional inductors, capacitors, interconnects, and other passive circuit elements. For example, conventional inductor 152 is typically formed as a two-dimensional masked metal deposition. Normally inductor 152 overlies the uppermost dielectric layer (represented by insulating layer 154) of SOI structure 150, where it is separated from substrate 106 by a distance D152.
Although one motivation for using conventional SOI structures is to reduce parasitic capacitance, parasitic capacitance persists between the substrate and the circuit elements in the active semiconductor layer. In particular, passive circuit elements, e.g. inductors, capacitors, and interconnects, which are dimensionally much larger than typical active devices, are accordingly more susceptible to the effects of parasitic capacitance. Whereas MOS active devices approach sub-0.5-micron (.mu.m) dimensions, passive devices, for example inductors, are unlikely to become smaller than hundreds of microns. Therefore, in high frequency wireless communication applications where passive circuit elements such as inductors are commonly required, these inductors are typically hundreds of time larger than any MOS active device.
The detrimental consequences of parasitic capacitance affect circuit performance by reducing the "Q" factor of passive components and increasing overall circuit loss. Parasitic capacitance also adds to any design capacitances, thus degrading circuit performance. These problems are particularly significant where the integrated circuit is operated at high frequencies, such as typically encountered in modern RF communication circuits and high speed digital integrated circuits.
For example, wireless RF communication devices are frequently high frequency, compact, and battery-powered. Circuit losses caused by parasitic capacitance increase the power dissipation of these devices. Power dissipation, in turn, increases the battery requirement, which leads to shorter battery life and/or larger batteries, increasing size, weight, cost, and inconvenience.
As a further example, a microprocessor or large memory chip with a high density of long interconnects has significant parasitic capacitance to the substrate, even when using current SOI technology. As future microprocessor clock frequencies increase, circuit losses due to parasitic capacitance will become an increasingly serious limitation. Parasitic capacitance also contributes significantly to RC propagation delay, further limiting microcomputer speed. As present microprocessor clock frequencies are over 300 megahertz and are predicted to reach the one gigahertz range within the next few years, reducing parasitic capacitance is important. Thus, reducing parasitic capacitance in SOI structures employed for RF and other high frequency applications is desirable.
One approach to reducing parasitic capacitance is to increase the distance (for example dimension D152 in FIG. 1B) between the passive circuit element (e.g. inductor 152) and substrate 106. However, as passive circuit elements are typically placed above the uppermost dielectric layer of a circuit (e.g. inductor 152 overlying insulating layer 154 in FIG. 1B), it is impractical to increase distance D152 simply by adding layers. Increasing the thickness of the active layer or existing insulating layers can also increase distance D152 However, as an increase in the active layer thickness will add parasitic capacitance to active devices, and an increase in the thickness of insulating layers will add undesired process complexity, neither of these alternatives is attractive.
A further approach is to increase the thickness of buried oxide layer 104. However, efforts to date have resulted in a maximum total thickness of only about 1 .mu.m for buried oxide layer 104.
Finally, an approach of electrically floating rather than grounding substrate 106 has been offered. This approach has shown some effectiveness for active devices at moderate frequencies. However, physically larger inductors and other passive circuit elements still exhibit parasitic capacitance and associated losses, particularly at higher frequencies. Substrate 106 effectively constitutes a common potential plane having nodes that capacitively couple the various circuit elements together, particularly as frequencies increase. Thus, substrate 106, although floating electrically at low frequencies, may not be effectively floating at high frequency. Losses also increase at high frequency, as the impedance associated with parasitic capacitance becomes increasingly resistive.
Conventional SOI technologies, therefore, have been found to offer a less than optimal solution for the remaining parasitic capacitance and its associated loss. Hence, it would be desirable to provide a method and structure that significantly reduce parasitic capacitance between circuit elements, particularly passive devices and interconnects. Such a method should be inexpensive, easy to implement without adding significant process complexity, and not detrimental to yields.